Adequately planarizing completed integrated circuits ("ICs") presents a formidable challenge when fabricating sub-micron devices, e.g., devices having &lt;1 .mu.m or 10,000 .ANG. horizontal distance between adjacent metal traces. Using well known techniques, ICs are fabricated on a substrate by forming various depositions, layer by layer. For example, an IC containing a metal-oxide-semiconductor ("MOS") device has a thin layer of oxide over which a polysilicon gate is deposited and defined, whereafter source and drain regions are implanted connecting the channel region underlying the gate.
A layer of inter-level dielectric ("ILD") is then formed atop the polysilicon level (and thus over the MOS or other device thereunder). A first level of metal traces is then deposited and defined atop the ILD. A layer of inter-metal-oxide ("IMO") may be formed atop the first level of metal traces, with an overlying second level of metal traces fabricated atop the IMO, for electrical communication though vias with underlying metal one traces.
FIG. 1A depicts generally what has been described, wherein the active device (shown generically as 10) is formed on substrate 20 and covered by ILD layer 30. The nature of device 10 is not important to the present invention, and it is understood that device 10 encompasses MOS, bipolar, bipolar-complementary MOS ("BiCMOS") devices, among others.
Several level one metal traces M1A, M1B, M1C are shown in FIG. 1A. These traces are insulated by an insulating IMO layer 40 from overlying level two metal traces, M2A, M2B. A via 50 is shown electrically coupling level one metal trace M1A with level two metal trace M2A.
The vertical height of the metal 1 traces creates an uneven topography that must be levelled or evened-out to permit a proper deposition of the metal 2 traces. Thus, IMO layer 40 provides electrical insulation between the metal 1 and metal 2 layers, and preferably also provides a planarizing function.
FIG. 2A provides further detail as to the formation of IMO layer 40. Preliminary, the IMO typically comprises at least two separate layers, namely layers 60 and 70, and after planarization is complete the IMO further comprises an additional cap layer 80 (see FIG. 2B). Layer 60 is typically tetra-ethyl-ortho-silicate ("TEOS")-based oxide, formed by plasma enhanced chemical vapor deposition ("PECVD"). Alternatively, layer 60 may be formed by a thermal CVD process using ozone (O.sub.3) as a reaction species. Next, a preferably thick layer of spin-on-glass ("SOG") 70 is spun onto the structure in liquid form to even-out the topography. As will be described, after SOG etch back, a conventional cap oxide layer 80 is formed over the planarized surface.
For ease of illustration in FIG. 2A (as well as FIGS. 2B, 3A, 3B), the upper surface of layer 30 is depicted in a substantially horizontal plane. In reality, due to underlying topography the upper surface of layer 30 may in fact undulate. As a result, the uppermost surface of some of the metal 1 traces may differ in height from one another. That is to say, for example, that the uppermost surface of M1C may in fact be at a higher level than the uppermost surface of M1A.
Due to the nature of the CVD process, the TEOS-based oxide layer 60 thickness will not depend upon the height of the top of the metal 1 traces. However the amount of SOG 70 atop the metal traces will depend upon the height of the TEOS-based oxide. Spin on characteristics of the liquid SOG are such that the thickness of the SOG 70 will depend upon the height of the underlying TEOS-based oxide layer. For example, if the upper surface of M1C were higher than the upper surface of M1A, the liquid nature of the SOG would result in more SOG being present atop M1A than would be present atop M1C.
To improve reliability of the via 50 and to improve the properties of the underlying device 10, the SOG 70 is then etched-back, for example to the depth noted by the phantom line D. Ideally level D is located at depth where no SOG remains above the metal 1 traces and the metal 1 traces are not exposed by the etching process. However, if too little SOG is etched away and the resultant depth is D" (see FIG. 2A), some SOG remains above the metal 1 traces M1A, M1B, M1C, and the reliability of via 50 and device 10 can be degraded, as will be described. Similarly, if too much SOG is etched away and the resultant depth is D', the metal 1 traces are exposed, which can degrade the planarization and affect the performance and yield of device 10.
As noted above, undulations can exist at the upper surface of layer 30 that result in variations in the height of the top of the metal 1 traces, and in variations of the thickness of the SOG overlying these traces. These variations in metal 1 heights and in SOG thicknesses impose even more stringent requirements in meeting the twin goals of leaving no SOG atop metal 1 traces, while not exposing the upper surface of any metal 1 traces during etch back. Understandably, the level of D' must be above the highest of the metal 1 traces.
Ensuring that the etch-back depth is D rather than D' or D" under all process scenarios is not a simple task in the prior art. In overview, a large layer 60 thickness (TEOS or equivalent) is desired to better protect the metal 1 traces against exposure during etching, e.g., against a D' scenario (see FIG. 2A). However as shown in FIG. 1C, if layer 60 is too thick, voids can result that degrade planarization and device 10 performance. Good planarization dictates that the SOG layer 70 be thick, with preferably as much SOG being is etched away as was deposited. Controlling the etch depth D is complicated because when the etching process exposes the TEOS-based oxide layer, oxygen atoms therein become liberated and accelerate the rate of SOG etching by about 100%. Thus, in practice the SOG layer should be about half the thickness of the TEOS-based oxide layer 60 to compensate for the differential etching rate between SOG and TEOS-based oxide, and for the variation in thickness of the SOG overlying metal 1 traces. These various considerations will now be described in detail.
The ability of layer 60 material to uniformly coat a metal trace, e.g., M1A, M1B, etc., is commonly referred to as step coverage. Ideally layer 60 (TEOS-based oxide or equivalent) should conform perfectly to the profile of the metal 1 trace, providing as much step coverage in the horizontal dimension as in the vertical dimension. In practice, however, while TEOS-based oxide is a relatively conformal material providing a non re-entrant profile, the sidewall coverage is only about 55% of the horizontal coverage. Stated differently, if the TEOS-based oxide deposited a layer 100 units thick atop the metal 1 trace, the sidewall coverage along the vertical wall of the metal 1 trace would be 55 units.
With respect to FIG. 1B, as the closest pitch distance Lx between adjacent metal 1 traces becomes smaller, the ability of layer 60 of thickness T1 to conformally coat the metal 1 profile horizontally and vertically becomes more important. This is especially true in structures wherein Lx is &lt;1 .mu.m or 10,000 .ANG. ("sub-micron" structures) and more so where Lx is &lt;0.5 .mu.m or 5,000 .ANG. ("deep sub-micron" structures). The step coverage depicted in FIG. 1B is acceptable, and provides a so-called non re-entrant profile, which means that no voids or gaps are formed in layer 60 between adjacent metal traces.
By contrast, FIG. 1C depicts a re-entrant profile situation with inadequate layer 60 step coverage. Such profiles can result where Lx is too small, or where layer 60's thickness T2 is too large relative to Lx. Re-entrant profiles are not acceptable because as the layer 60 material fills the narrow "valley" between adjacent metal traces M1A and M1B, a narrow gap 90 can form. If too narrow, such gaps 90 are not filled by the subsequently applied SOG layer 70, and the resultant voids can detrimentally affect planarization and device 10 performance. It is for this reason that chemical vapor deposition of SiH.sub.4 -based films cannot be used in sub-micron structures.
FIG. 2B depicts the ideal case where the structure of FIG. 2A has had the SOG layer 70 etched-back to the level defined by D. A conventional cap oxide layer 80 that may be TEOS-based oxide or SiH.sub.4 -based oxide is then formed over the planarized surface defined by level D. Via 50 and metal layer 2 traces may then be formed. It will be appreciated that cap oxide layer 80 advantageously prevents a metal 2 trace from detrimentally being in direct contact with SOG 70. Thus, after planarization is complete and before any metal 2 traces or vias 50 are formed, IMO 40 comprises typically three layers, namely layers 60, 70 and 80.
It is important to appreciate from FIG. 2B that after etch-back to level D, pockets of SOG 70 that fill voids between adjacent metal 1 traces may remain, but no SOG is permitted to remain over a metal 1 trace. SOG overlying a metal 1 trace can cause formation of positive charges that can degrade device reliability and degrade hot carrier device characteristics. Further, where a via is to couple a metal 1 trace to an overlying metal 2 trace (see for example via 50 in FIG. 1A), any intervening SOG overlying the metal 1 trace could outgas during via metal deposition, degrading via reliability.
Unfortunately, variations in the thickness of the SOG layer 70 or TEOS-based oxide layer 60, as well as variations in the etch-back process create uncertainty as to where precisely the D level will end up. For example, on a flat wafer region the thickness of the SOG layer 70 can vary perhaps .+-.5% and on a non-flat region can vary almost from zero .ANG. to the nominal thickness of the SOG overlying a metal trace, and the TEOS-based oxide layer thickness can vary perhaps .+-.3%. The etcher mechanism itself may contribute .+-.5% variation in the etching process. Day-to-day wafer variations can contribute another .+-.10% uncertainty to the etch-back process. Further, the SOG etch rate is especially sensitive to wafer temperature and etch chamber cleanliness.
In practice, to maintain the location of the D level in a desired range (e.g., so that neither metal 1 traces are exposed nor does SOG 70 remain atop a metal 1 trace) requires controlling etch uniformity within one sigma of .+-.5%. This .+-.5% or more uncertainty in the etch-back process, combined with variations in the depth of the SOG layer, means that too little SOG, or too much SOG and TEOS-based oxide may be removed. Stated differently, the margin of error associated with etching-back must not result in the removal of too little SOG, or too much SOG and TEOS-based oxide.
With reference to FIG. 2A, removing too little SOG could put the etched-back surface not at level D but at level D", a condition wherein SOG undesirably remains over the metal 1 traces. On the other hand, removing too much SOG and TEOS-based oxide could put the etched-back surface not at level D but at level D', a condition undesirably exposing the metal 1 traces. Exposing the metal 1 traces would result in degraded planarization and degraded device 10 performance and yield.
As such, D" and D' demark just beyond the acceptable margin of error tolerances associated with the etch-back process. If D' were sightly shallower as to not expose the metal 1 traces, or if D" were slightly deeper as to remove all SOG overlying the metal 1 traces, the etch-back process would be operating within an acceptable margin of error.
Reliably ensuring that etch-back halts at the D level is complicated by the fact that the SOG etch rate is not constant. With reference to FIG. 2A, SOG etching typically proceeds at a constant rate through the level D", since only one type of material is being etched, SOG 70. However, as soon as the etching process begins to expose the underlying TEOS-based oxide layer 60, the rate of SOG etch increases substantially. This acceleration in the SOG etch rate results from the presence of oxygen atoms that are liberated from the exposed TEOS-based oxide layer.
To maintain good planarization, it is necessary to compensate for this accelerated etch phenomenon. It is known in the prior art that making the etch rate for the TEOS-based oxide layer 60 about twice the etch rate for the SOG can compensate for these etch effects. In practice, a typical etch-back rate for SOG (in the absence of liberated oxygen atoms) might be 50 .ANG./second, whereas the etch-back rate for TEOS-based oxide is about 100 .ANG./second. However, as the etch-exposed TEOS-based oxide liberates oxygen atoms, the SOG etch rate increases to about 100 .ANG./second, with the result that both the SOG and TEOS-based oxide materials then etch at about the same rate.
This differential etch-back rate further implies that to remove, say, a 3,000 .ANG. thick layer of SOG, the TEOS-based oxide layer 60 should be at least 6,000 .ANG. thick. Understandably, increasing the thickness of the TEOS-based oxide layer can ensure that the metal 1 traces are never exposed, thus providing an increased margin of error for the etch-back process. Unfortunately, however, too thick a TEOS-based oxide layer 60 can result in voids 90 in sub-micron devices, as suggested by FIG. 1C.
Thus, in practice, where the metal 1 traces have a vertical thickness on the order of 0.7 .mu.m (7,000 .ANG.), and where Lx is approximately 0.5 .mu.m (5,000 .ANG.), the TEOS-based oxide 60 layer cannot be thicker than about 5,000 .ANG. to about 7,000 .ANG.. A 5,000 .ANG. to 7,000 .ANG. thick TEOS-based oxide layer dictates that the SOG layer should be about 2,500 .ANG. to about 3,000 .ANG. thick, e.g., about half the TEOS-based oxide thickness. In practice, for metal traces horizontally spaced less than about 1 .mu.m apart, 3,000 .ANG. is approximately the thickest layer of SOG than can be spun-on to achieve good planarization.
However, as noted, uncertainties in the etching process may readily cause perhaps 15%.times.3,000 .ANG., or .+-.900 .ANG. (three sigma) too little or too much SOG to be removed. Although the prior art attempts to carefully control the margin of error associated with the etch-back process, the end result is still a very narrow process window.
What is needed is a method of providing a greater useful margin of error in the etch-back planarization of submicron devices. Such method should provide a buffer mechanism that inhibits plasma oxide etch rate as the etching process approaches the metal 1 traces. Preferably such method should be compatible with existing fabrication processes, and should improve yield and device reliability.
The present invention discloses such a method.